Derek R. Hower, Bradford M. Beckmann, Benedict R. Gaster, Blake A. Hechtman, Mark D. Hill, Steven K. Reinhardt, and David A. Wood
Workshop on Memory Systems Performance and Correctness (MSPC). June 2013
Hardware vendors now provide heterogeneous platforms in commodity markets (e.g., integrated CPUs and GPUs), and are promising an integrated, shared memory address space for such platforms in future iterations. Because not all threads in a heterogeneous platform can communicate with the same latency, vendors are proposing synchronization mechanisms that allow threads to communicate with a subset of threads (called a scope). However, vendors have yet to define a comprehensive and portable memory model that programmers can use to reason about scopes. Moreo- ver, existing CPU memory models, such as Sequential Consistency for Data-Race-Free (SC for DRF), are ill-suited, in part, because they define all synchronization operations globally and preclude low-energy, high-performance local coordination.
Towards this end, we embrace scoped synchronization with a new class of memory consistency models: Sequen- tial Consistency for Heterogeneous-Race-Free (SC for HRF). Inspired by SC for DRF (C++, Java), the new mod- els provide programmers with SC for programs with “suffi- cient” synchronization (no data races) of “sufficient” scope. We develop the first such model, called HRF0, show how it can be used to develop high-performance code, show ex- ample hardware support, and motivate future work.